RISC-V is a free, open, extensible instruction set architecture (ISA), the specification is now maintained by the nonprofit RISC-V Foundation.
StarFive produces a number of RISC-V SoCs, mostly based on the SiFive designs. Upstreaming the device / interface support for them is in progress.
| Target | CPU | Series | CPU cores | CPU MHz | Notes |
|---|---|---|---|---|---|
| starfive | JH7100 | U74 | 2 | 1.0GHz | RV64GC |
| starfive | JH7110 | U74 | 4 | 1.5GHz | RV64GC |
CPU datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
CPU datasheet: https://doc-en.rvspace.org/JH7110/PDF/JH7110_Datasheet.pdf